1. Overview
Rev.1.00 Jan. 10, 2008 Page 8 of 1658
REJ09B0261-0100
Item Features
PCI bus controller
(PCIC)
PCI bus controller (supports a subset of revision 2.2)
32-bit bus (33 MHz or 66 MHz)
Operation as PCI master/target
Operation in PCI host/normal mode
Built-in bus arbiter (host mode)
Operates with up to four external bus-master devices
Mode for operation with an external bus arbiter
Supports burst transfers
Supports parity checking and error reports
Supports four individual external interrupt signals (INTA to INTD) in host
mode
Supports a single external interrupt signal (INTA) in normal mode
Up to 512 Mbytes of PCI memory space (32 bit address mode)
Up to 64 Mbytes of PCI memory space (29 bit address mode)
Direct memory
access controller
(DMAC)
Number of channels: 12
12-channel physical address DMA controller
Four channels support external requests (channels 0 to 3)
Address space: 4 Gbytes (Physical address)
Units of data transfer: 8, 16, or 32 bits; 16 or 32 bytes
Address modes:
Dual address mode
Transfer requests: External request, on-chip peripheral module request,
or auto-request
Choice of DACK or DRAK (four external pins)
Bus modes: Cycle-stealing or burst mode
Priority: Select either fixed mode or round-robin mode
Clock pulse
generator (CPG)
CPU frequency: Up to 600 MHz
Local bus frequency: Up to 100 MHz
DDR2-SDRAM interface frequency: Up to 300 MHz
On-chip peripheral bus frequency: Up to 50 MHz
Power-down modes
Sleep mode
Module-standby mode
DDR back-up power function (power is supplied only to the DDR)