4. Pipelining

Rev.1.00 Jan. 10, 2008 Page 68 of 1658

REJ09B0261-0100

I3
I3
I3
I1 I2 ID s1 s2 s3 WB
I1 I2 ID WB
I1 I2 ID E1/S1 E2/s2 E3/s3
E1/s1 E2/s2 E3/S3
WB
I1 I2 I3 ID E1 E2 E3 WB
(2-1) 1-step operation (EX type): 1 issue cycle
(2-2) 1-step operation (LS type): 1 issue cycle
(2-3) 1-step operation (MT type): 1 issue cycle
(2-4) MOV (MT type): 1 issue cycle
EXT[SU].[BW], MOVT, SWAP, XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#,
NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, CLRS, CLRT, SETS, SETT
MOV#, NOP
MOVA
MOV
Note: Except for AND#, OR#, TST#, and XOR# instructions using GBR relative
addressing mode
Figure 4.2 Instruction Execution Patterns (2)