Renesas SH7781 - page 1010

20. Graphics Data Translation Accelerator (GDTA)
Rev.1.00 Jan. 10, 2008 Page 980 of 1658
REJ09B0261-0100
20.3.2 GA Enable Register (GACER)
GACER is in the GDTA common register block and controls the block operation.
161718192021222324252627282931 30
0000000000000000
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
BIt:
Initial value:
R/W:
01234567891011121315 14
0000000000000000
CL_ENMC_EN ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
R/WR/W⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 2 ⎯ All 0 ⎯ Reserved
These bits are always read as 0. The write value should
always be 0.
1 MC_EN 0 R/W Enables access to the MC registers.
0: Writing to the MC registers is invalid. The value read
from the MC register is undefined.
1: Reading and writing are enabled.
0 CL_EN 0 R/W Enables access to the CL registers.
0: Writing to the CL registers is invalid. The value read
from the CL register is undefined.
1: Reading and writing are enabled.