13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 610 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
2 MAIM 0 SH: R/WC
PCI: R
Master-Abort Interrupt Mask
0: MAI disabled (masked)
1: MAI enabled (not masked)
1 RDPEIM 0 SH: R/WC
PCI: R
Read Data Parity Error Interrupt Mask
0: RDPEI disabled (masked)
1: RDPEI enabled (not masked)
0 WDPEIM 0 SH: R/WC
PCI: R
Write Data Parity Error Interrupt Mask
0: WDPEI disabled (masked)
1: WDPEI enabled (not masked)
(12) PCI Arbiter Bus Master Information Register (PCIBMIR) In host mode, this register records when the interrupt is generated by PCIAINT. When multiple interrupts occur, only the first source is registered. When an interrupt is disabled, the source is registered in the corresponding bit, and no interrupt occurs.
SH R/W:
PCI R/W:
SH R/W:
PCI R/W:
161718192021222324252627282931 30Bit:
Initial value:
RRRRRRRRRRRRRRRR
RRRRRRRRRRRRRRRR
0000000000000000
——
RRRRRRRRRRRRRRRR
RRRRRRRRRRRRRRRR
xxxxx00000000000
PCIC
BME
REQ0
BME
REQ1
BME
REQ2
BME
REQ3
BME
——
01234567891011121315 14Bit:
Initial value: