Appendix
Rev.1.00 Jan. 10, 2008 Page 1646 of 1658
REJ09B0261-0100
Pin Name (LSI level)
Pin Name
(Module level) Module I/O When Not in Use
PCIFRAME PCIC I/O
VSYNC DU I/O
PCIFRAME/
VSYNC
Port P0 GPIO I/O
Open*2
IDSEL IDSEL PCIC I Pulled-down to VSS
INTA PCIC I/O INTA
Port Q4 GPIO I/O
Open*2 or pulled-up to VDDQ
when PCIC normal mode
IRDY PCIC I/O
HSYNC DU I/O
IRDY/HSYNC
Port P1 GPIO I/O
Open*2
LOCK PCIC I/O
ODDF DU I/O
LOCK/ODDF
Port P3 GPIO I/O
Open*2
PAR PAR PCIC I/O Open*2
PCICLK PCIC I PCICLK/
DCLKIN DCLKIN DU I
When the bus mode selected
by MODE11 and MODE12
pins is a PCI host bus bridge
or a PCI normal (non-host)
mode, clock must be input to
the PCICLK pin.
When the bus mode selected
by MODE11 and MODE12
pins is a Local bus or Display
Unit mode, PCICLK pin must
be pulled-up to VDDQ or
pulled-down to GND.
PCIRESET PCIRESET PCIC O Open
PERR PCIC I/O PERR
Port Q1 GPIO I/O
Open*2
SERR PCIC I/O SERR
Port Q0 GPIO I/O
Open*2
STOP/CDE STOP PCIC I/O Open*2
CDE DU O
Port P4 GPIO I/O