Renesas SH7781 Figure 32.42 SCIFn_CLK Input Clock Timing

32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1603 of 1658
REJ09B0261-0100
32.3.9 SCIF Module Signal Timing
Table 32.14 SCIF Module Signal Timing
Conditions: VDDQ= 3.0 to 3.6 V, VDD= 1.1 V, Ta= −40 to 85°C, CL= 30 pF, PLL2 on
Module Item Symbol Min. Max. Unit Figure
SCIFn Input clock cycle (asynchronous) tScyc 4 — tPcyc
Input clock cycle (clock synchronous) 10 — tPcyc
Input clock pulse width tSCKW 0.4 0.6 tScyc
Input clock rise time tSCKr — 0.8 tPcyc
Input clock fall time tSCKf — 0.8 tPcyc
32.42
Transfer data delay time tTXD — 6 tPcyc 32.43
Receive data setup time
(clock synchronous)
tRXS 16 — ns
Receive data hold time
(clock synchronous)
tRXH 16 — ns
Note: tpcyc means one cycle time of the peripheral clock (Pck).
t
SCKW
t
Scyc
t
SCKf
t
SCKr
SCIFn_CLK
Figure 32.42 SCIFn_CLK Input Clock Timing