13. PCI Controller (PCIC)

Rev.1.00 Jan. 10, 2008 Page 639 of 1658

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31 0
A
31 0
A
31 0
A
31 0
A
B B B B
C C C C
D D D D
AB AB BA AB
CD CD DC CD
CDAB CD DC CDAB ABBA
Size
Byte
Word
long-
word
Address
4n + 0
4n + 1
4n + 2
4n + 3
4n + 0
4n + 2
4n + 0
SHwy bus
PCI bus
Big-endian CPU
Data Data (without swapping) Data (with swapping)
Little-endian CPU
Figure 13.9 Data Alignments for SuperHyway Bus and PCI Bus