13. PCI Controller (PCIC)

Rev.1.00 Jan. 10, 2008 Page 642 of 1658

REJ09B0261-0100

MBARE
PCI address
31 28 20 0 29 19
PCIMBAR0/1
PCILSR0/1
PCILAR0/1
SHwy bus
address
Compare
0
31 20 0
29
0
31 28 20 0 29 19
1928
31 2029 1928
31 2029 1928
Figure 13.11 PCI Bus to SuperHyway Bus Address Translation (2) Accessing PCIC I/O Space The PCI I/O address space should be allocated as 256 bytes. The lower eight bits ([7:0]) are sent to the internal bus without translation. When bits 31 to 8 of a PCI address match bits 31 to 8 of PCIIBAR, the upper 24 bits are replaced with H'FE04 01 and a PCI local register is accessed.
PCI address
PCI address
SHwy bus address
31 8 7 0
31 8 7 0
31 8 7 0
Compare
H'FE0401
Figure 13.12 I/O Access from PCI Bus to SuperHyway Bus