Renesas SH7781 32.3.17 FLCTL Module Signal Timing Table 32.22 NAND-Type Flash Memory Interface Timing

32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1618 of 1658
REJ09B0261-0100
32.3.17 FLCTL Module Signal Timing
Table 32.22 NAND-Type Flash Memory Interface Timing
Item Symbol Min. Max. Unit Figure
Command issue setup time tNCDS 2 × tfcyc −10 — ns
Command issue hold time tNCDH 1.5 × tfcyc −10 — ns
32.67, 32.71
Data output setup time tNDOS 0.5 tfcyc −10 — ns
Data output hold time tNDOH 0.5 tfcyc −10 — ns
32.67, 32.68,
32.70, 32.71
Command to address transition time 1 tNCDAD1 1.5 × tfcyc −10 — ns 32.67, 32.68
Command to address transition time 2 tNCDAD2 2 × tfcyc −10 — ns 32.68
FWE cycle time tNWC t
fcyc −5 — ns 32.68, 32.70
FWE low pulse width tNWP 0.5 tfcyc −5 — ns 32.67, 32.68,
32.70, 32.71
FWE high pulse width tNWH 0.5 tfcyc −5 — ns 32.68, 32.70
Address to ready/busy transition time tNADRB — 32 × tpcyc ns 32.68, 32.69
Ready/busy to data read transition
time 1
tNRBDR1 1.5 × tfcyc — ns
Ready/busy to data read transition
time 2
tNRBDR2 32 × tpcyc — ns
FSC cycle time tNSCC t
fcyc — ns
FSC high pulse width tNSPH 0.5 × tfcyc −5 — ns
32.69
FSC low pulse width tNSP 0.5 × tfcyc −5 — ns
Read data setup time tNRDS 24 — ns
Read data hold time tNRDH 5 — ns
32.69, 32.71
Data write setup time tNDWS 32 × tpcyc −10 — ns 32.70
Command to status read transition
time
tNCDSR 4 × tfcyc −10 — ns 32.71
Command output off to status read
transition time
tNCDFSR 3.5 × tfcyc — ns
Status read setup time tNSTS 2.5 × tfcyc −10 ns
Notes: 1. tpcyc is the period of one peripheral clock (Pck) cycle.
2. tfcyc is the period of one FLCTL clock (Fck) cycle.