22. Serial I/O with FIFO (SIOF)
Rev.1.00 Jan. 10, 2008 Page 1110 of 1658
REJ09B0261-0100
22.3.5 Transmit Control Data Register (SITCR) SITCR is a 32-bit readable/writable register that specifies transmit control data of the SIOF. The setting of SITCR is valid only when bits FL3 to FL0 in SIMDR are set to 1xxx (x: any value). SITCR is initialized by the conditions shown in table 22.3, Register State in Each Operating Mode, or by a transmit reset by the TXRST bit in SICTR.
161718192021222324252627282931 30
——
SITC0[15:0]
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W R/W
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W R/W
BIt:
Initial value:
R/W:
01234567891011121315 14
——
SITC1[15:0]
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 16 SITC0[15:0] H'0000 R/W Control Channel 0 Transmit Data
These bits specify data to be output from the
SIOF_TXD pin as control channel 0 transmit data. The
position of the control channel 0 data in the transmit or
receive frame depends on the value set in the CD0A bit
in SICDAR.
These bits are valid when the CD0E bit in SICDAR
is set to 1.
15 to 0 SITC1[15:0] H'0000 R/W Control Channel 1 Transmit Data
These bits specify data to be output from the
SIOF_TXD pin as control channel 1 transmit data. The
position of the control channel 1 data in the transmit or
receive frame depends on the CD1A bit in SICDAR.
These bits are valid when the CD1E bit in SICDAR
is set to 1.