17. Power-Down Mode
Rev.1.00 Jan. 10, 2008 Page 784 of 1658
REJ09B0261-0100
Table 17.4 Register States of CPG in Each Processing Mode
Power-on Reset Manual Reset
Sleep/
Deep Sleep
Register Name Abbreviation
By PRESET
Pin/WDT/H-UDI By WDT
By SLEEP
Instruction
Standby control register 0*1 MSTPCR0 H'0000 0000 Retained Retained
Standby control register 1*1 MSTPCR1 H'0000 0000 Retained Retained
Standby display register MSTPMR H'00x0 00002 Retained Retained
Notes: 1. For details of MSTPCR0 and MSTPCR1, see figure 15.1.
2. The initial value after a power-on reset depends on the combination of mode pin states
(MODE11 and MODE12).
If a low level signal is input to the MODE12 pin, the initial value is H'0010 0000.
If a high level signal is input to the MODE12 pin and a low level signal is input to
MODE11, the initial value is H'0030 0000.
If a high level signal is input to the MODE12 and MODE11 pins, the initial value is
H'0020 0000.