19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 830 of 1658
REJ09B0261-0100
Table 19.3 Status of Registers in Each Processing Mode
Register Name Abbr.
Power-On
Reset by
PRESET
Pin/ WDT/
H-UDI
Manual
Reset by
WDT
Sleep by
Sleep
Instruction
Module
Standby
Deep
Sleep
Bits with
Internal Update
Function
Display control registers
Display system
control register
DSYSR H'00000280 Retained Retained Retained Retained DSEC
DEN
Display mode
register
DSMR H'00000000 Retained Retained Retained Retained All bits
except the
following bits
which are
updated by the
DRES bit in the
display system
control register
(DSYSR):
VSPM
ODPM
DIPM
CSPM
DIL
VSL
HSL
Display status
register
DSSR H'30000000 Retained Retained Retained Retained None
Display status
register clear
register
DSRCR Undefined Retained Retained Retained Retained None
Display interrupt
enable register
DIER H'00000000 Retained Retained Retained Retained None
Color palette
control register
CPCR H'00000000 Retained Retained Retained Retained All bits
Display plane
priority order
register
DPPR H'00543210 Retained Retained Retained Retained All bits
Display extension
function enable
register
DEFR H'00000000 Retained Retained Retained Retained None