10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 287 of 1658
REJ09B0261-0100
(7) Interrupt Mask Register 2 (INTMSK2) INTMSK2 is a 32-bit readable and conditionally writable register that sets masking for IRL interrupt requests for input level pattern on the IRL pins. To clear the mask setting for the interrupt, write 1 to the corresponding bit in INTMSKCLR2. Writing 0 to the bits in INTMSK2 has no effect. By reading this register once after writing to this register or after clearing the mask by setting IMTMSKCLR2, the time length necessary for reflecting the register value can be assured (the value read is reflected to the mask status). INTMSK2 settings are valid when the IRQ/IRL3 to IRQ/IRL0 pins or IRQ/IRL7 to IRQ/IRL4 pins are used for encoded IRL interrupt inputs, and the corresponding IRL interrupt is not masked by INTMSK1.
161718192021222324252627282931 30
0000000000000000
IM001IM002IM003IM004IM005
IM006IM007IM008IM009
IM010IM011IM012IM013
IM015IM014
RR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W R/W
RR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W R/W
Bit:
Initial value:
R/W:
01234567891011121315 14
0000000000000000
IM101IM102IM103IM104IM105IM106IM107IM108IM109IM110IM111IM112IM113IM115IM114
Bit:
Initial value:
R/W:
Bit Name
Initial
Value R/W Description
31 IM015 0 R/W Masks the interrupt source
of IRL3 to IRL0 = LLLL
(H'0).
30 IM014 0 R/W Masks the interrupt source
of IRL3 to IRL0 = LLLH
(H'1).
29 IM013 0 R/W Masks the interrupt source
of IRL3 to IRL0 = LLHL
(H'2).
[When read]
0: The interrupt is
accepted.
1: The interrupt is
masked.
[When written]
0: No effect
1: Masks the interrupt
28 IM012 0 R/W Masks the interrupt source
of IRL3 to IRL0 = LLHH
(H'3).
27 IM011 0 R/W Masks the interrupt source
of IRL3 to IRL0 = LHLL
(H'4).