Appendix
Rev.1.00 Jan. 10, 2008 Page 1635 of 1658
REJ09B0261-0100
Reset
Pin Name
(LSI level)
Pin Name
(Module level)
Related
Module I/O
Power
-on Manual Sleep
Module
Standby
Bus
Release
GNT3 PCIC O PZ K K K
MMCCLK MMCIF O PZ K K K K
GNT3/
MMCCLK *3
Port E0 GPIO I/O PZ K K K
GNT[2:1] PCIC O PZ K K K GNT[2:1] *3
Port E1-E2 GPIO I/O PZ K K K
REQ0/
REQOUT
PCIC I/O PZ K K K REQ0/REQOUT*3
Port Q2 GPIO I/O PZ K K K
REQ3 PCIC I PZ K K K REQ3*3
Port E3 GPIO I/O PZ K K K
REQ[2:1] PCIC I PZ K K K REQ[2:1] *3
Port E4-E5 GPIO I/O PZ K K K
DEVSEL PCIC I/O PZ K K K
DCLKOUT DU O PZ K K K
DEVSEL/
DCLKOUT*3
Port P5 GPIO I/O PZ K K K
PCIFRAME PCIC I/O PZ K K K
VSYNC DU I/O PZ K K K
PCIFRAME/
VSYNC*3
Port P0 GPIO I/O PZ K K K
IDSEL IDSEL PCIC I I I K I
INTA PCIC I/O PZ K K K INTA*3
Port Q4 GPIO I/O PZ K K K
IRDY PCIC I/O PZ K K K
HSYNC DU I/O PZ K K K
IRDY/HSYNC*3
Port P1 GPIO I/O PZ K K K
LOCK PCIC I/O PZ K K K
ODDF DU I/O PZ K K K
LOCK/ODDF*3
Port P3 GPIO I/O PZ K K K
PAR PAR PCIC I/O PZ O K O
PCICLK PCIC I I PI K K PCICLK/
DCLKIN*4 DCLKIN DU I I PI K K