26. Serial Sound Interface (SSI) Module

Rev.1.00 Jan. 10, 2008 Page 1330 of 1658

REJ09B0261-0100

(2) Transmission using Interrupt Data Flow Control
Start
End
Release reset,
specify configuration bits
in SSICR
Enable SSI module,
enable DMA,
enable error interrupts
Wait for Idle interrupt
from SSI module
Disable SSI module,
disable DMA
disable error interrupt,
enable Idle interrupt
Wait for interrupt from SSI
Use SSI status register bits
to realign data
after underflow/overflow
Load data of channel n
n = ( (CHNL + 1) x 2)
Loop
Next Channel
Data interrupt?
More data
to be send?
Specify TRMD, EN, SCKD,
SWSD, MUEN, DEL, PDTA,
SDTA, SPDP, SWSP, SCKP,
SWL, DWL, CHNL
EN = 1,
DIEN = 1,
UIEN = 1, OIEN = 1
EN = 0,
DIEN = 0
UIEN = 0, OIEN = 0,
IIEN = 1
No
No
Yes
Yes
Figure 26.22 Transmission Using Interrupt Data Flow Control