Renesas SH7781 - page 522

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 492 of 1658
REJ09B0261-0100
12.4.6 SDRAM Timing Register 1 (DBTR1)
The SDRAM timing register 1 (DBTR1) is a readable/writable register. It is initialized only upon
power-on reset.
161718192021222324252627282931 30
1000000000000000
TRP0TRP1TRP2 ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
R/WR/WR/WRRRRRRRRRRRRR
BIt:
Initial value:
R/W:
01234567891011121315 14
1000000000000000
TWR0TWR1TWR2 ⎯⎯⎯⎯⎯ TRRD0TRRD1TRRD2 ⎯⎯⎯⎯⎯
R/WR/WR/WRRRRRR/WR/WR/WRRRRR
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 19 ⎯ All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
18 to 16 TRP2 to
TRP0
001 R/W tRP (PRE-ACT/REF period) Setting Bits
These bits set the PRE-ACT minimum period constraint
for the same bank. These bits should be set according
to the DDR2-SDRAM specifications. The number of
cycles is the number of DDR clock cycles.
000: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
001: 2 cycles
010: 3 cycles
011: 4 cycles
100: 5 cycles
101: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
:
111: Setting prohibit (If specified, correct operation
cannot be guaranteed.)