Renesas SH7781 32.3.1 Clock and Control Signal Timing Table 32.6 Clock and Control Signal Timing

32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1568 of 1658
REJ09B0261-0100
32.3.1 Clock and Control Signal Timing
Table 32.6 Clock and Control Signal Timing
Item Symbol Min. Max. Unit Figure
Divider 1: × 1, PLL1: × 72,
PLL2 in operation*4
fEX 12 17 MHz EXTAL clock
input frequency
Divider 1: × 1, PLL1: × 36,
PLL2 in operation*6
23 34
Divider 1: × 1, PLL1: × 72,
PLL2 in operation*4
tEXcyc 59 83 ns 32.1 EXTAL clock
input cycle time
Divider 1: × 1, PLL1: × 36,
PLL2 in operation*6
29 43
EXTAL clock input low pulse width tEXL 3.5 ⎯ ns 32.1
EXTAL clock input high pulse width tEXH 3.5 ⎯ ns 32.1
EXTAL clock input rise time tEXr ⎯ 4 ns 32.1
EXTAL clock input fall time tEXf ⎯ 4 ns 32.1
CLKOUT clock output (with use of PLL1/PLL2) fOP 25 101 MHz
CLKOUT clock output cycle time tCKOcyc 10 1000 ns 32.2
CLKOUT clock output low pulse width tCKOL1 1 ⎯ ns 32.2
CLKOUT clock output high pulse width tCKOH1 1 ⎯ ns 32.2
CLKOUT clock output rise time tCKOr ⎯ 3 ns 32.2
CLKOUT clock output fall time tCKOf ⎯ 3 ns 32.2
CLKOUT clock output low pulse width tCKOL2 3 ⎯ ns 32.3
CLKOUT clock output high pulse width tCKOH2 3 ⎯ ns 32.3
Power-on oscillation settling time tOSC1 10 ⎯ ms 32.4
Power-on oscillation settling time/mode
(MODE14, MODE10, MODE9, MODE4 to
MODE0) settling time
tOSCMD 10 ⎯ ms 32.4
MODE (MODE13 to MODE11, MODE8 to
MODE5) reset setup time
tMDRS 3 ⎯ t
cyc 32.6