17. Power-Down Mode
Rev.1.00 Jan. 10, 2008 Page 791 of 1658
REJ09B0261-0100
17.3.4 Standby Display Register (MSTPMR) MSTPMR is a 32-bit readable register that indicates whether the PCIC/display unit (DU)/DMAC/GDTA modules are in the module standby state. MSTPMR can be accessed only in longword. This register is initialized by a power-on reset by the PRESET pin, power-on reset by WDT overflow, or H-UDI reset.
161718192021222324252627282931 30
0000xx0000000000
MSTP
MDU
MSTP
MPCI
⎯⎯
RRRRRRRRRRRRRRRR
BIt:
Initial value:
R/W:
01234567891011121315 14
0000000000000000
MSTPS
100
MSTPS
104
MSTPS
105
⎯⎯
RRRRRRRRRRRRRRRR
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 22 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
21 MSTPMPCI x R Module Stop Display Bit PCIC
Indicates the state of clock supply to the PCIC module
When a high level signal is input to the MODE12 pin,
the clock supply to the PCIC is stopped
0: PCIC operates (MODE12 pin: Low level)
1: PCIC stopped (MODE12 pin: High level)
20 MSTPMDU x R Module Stop Display Bit DU
Indicates the state of clock supply to the DU module.
When a low level signal is input to the MODE12 or
MODE11 pin, the clock supply to the DU is stopped.
0: DU operates (MODE[12:11] pin: All High level)
1: DU stopped (MODE[12:11] pin: Not all High level)
19 to 6 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.