32. Electrical Characteristics

Rev.1.00 Jan. 10, 2008 Page 1571 of 1658

REJ09B0261-0100

VDD
t
OSC1
V
DD
min
t
MDRH
t
OSCMD
t
TRSTRH
t
RESW
CLKOUT
Notes: 1. Oscillation settling time for the case when the on-chip resonator is used
2. PLL2 is operating
PRESET
MODE14
MODE10
MODE9
MODE4 to MODE0
TRST
Oscillation settling time
Internal clock
Figure 32.4 Power-On Oscillation Settling Time

CLKOUT

output

EXTAL

input

t

PLL

Figure 32.5 PLL Synchronization Settling Time