Renesas SH7781 Figure 32.41 TCLK Input Timing

32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1602 of 1658
REJ09B0261-0100
32.3.8 TMU Module Signal Timing
Table 32.13 TMU Module Signal Timing
Conditions: VDDQ= 3.0 to 3.6 V, VDD= 1.1 V, Ta= −40 to 85°C, CL= 30 pF, PLL2 on
Module Item Symbol Min. Max. Unit Figure Remarks
TMU Timer clock pulse width
(high)
tTCLKWH 4 — tPcyc 32.41
Timer clock pulse width
(low)
tTCLKWL 4 —
Timer clock rise time tTCLKr — 0.8
Timer clock fall time tTCLKf — 0.8
Note: tPcyc is the period of one peripheral clock (Pck) cycle.
t
TCLKWH
t
TCLKWL
t
TCLKf
t
TCLKr
TCLK
Figure 32.41 TCLK Input Timing