12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 482 of 1658
REJ09B0261-0100
12.4.1 DBSC2 Status Register (DBSTATE) The DBSC2 status register (DBSTATE) is a read-only register. Writing is invalid. It is initialized only upon power-on reset.
161718192021222324252627282931 30
0000000000000000
⎯⎯
RRRRRRRRRRRRRRRR
BIt:
Initial value:
R/W:
01234567891011121315 14
00000000x*0000000
ENDN⎯⎯
RRRRRRRRRRRRRRRR
BIt:
Initial value:
R/W:
Note: * Initial value is specified by external pin MODE8.
Bit Bit Name
Initial
Value R/W Description
31 to 9 All 0 R Reserved
These bits are always read as 0.
8 ENDN ×* R Endian Display Bit
Displays the endian of the DBSC2 set by external pin
MODE8.
0: Big endian
1: Little endian
7 to 0 All 0 R Reserved
These bits are always read as 0.
Note: * Initial value is specified by external pin MODE8.