Renesas SH7781 - page 777

15. Clock Pulse Generator (CPG)
Rev.1.00 Jan. 10, 2008 Page 747 of 1658
REJ09B0261-0100
15.4.4 PLL Control Register (PLLCR)
PLLCR is a 32-bit readable/writable register that controls the clock output on the CLKOUT pin.
This register can only be accessed in longwords.
161718192021222324252627282931 30
0000000000000000
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
R/WR/WR/WR/WR/WR/WR/WR/WRRRRRRRR
BIt:
Initial value:
R/W:
01234567891011121315 14
0000000000000000
⎯
CKOFF ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
RR/WRRRRRRRRRRRRRR
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 24 ⎯ 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
23 to 16 ⎯ All 0 R/W Reserved
These bits are always read as 0. The write value
should always be 0. If a value other than 0 is written,
the operation is not guaranteed.
15 to 2 ⎯ All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
1 CKOFF 0 R/W CLKOUT Output Enabled
Stops clock output on the CLKOUT pin
0: Clock is output on the CLKOUT pin
1: The CLKOUT pin is placed in the high impedance
state
0 ⎯ 0 R Reserved
This bit is always read as 0. The write value should
always be 0.