12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 491 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
2 to 0 TRCD2 to
TRCD0
001 R/W tRCD (ACT-READ/WRITE period) Setting Bits
These bits set the ACT-READ/WRITE minimum period.
These bits should be set according to the DDR2-
SDRAM specifications. The number of cycles is the
number of DDR clock cycles.
000: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
001: 2 cycles
010: 3 cycles
011: 4 cycles
100: 5 cycles
101: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
:
111: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
Notes: 1. AL (Additiv e Latency) supported by the DBSC2 is only 0.
2. Writing to this register should be performed only when the following conditions are met.
When SDRAM access is disabled (when the ACEN bit in the DBEN register is 0.).
When automatic issue of auto-refresh is disabled (when the ARFEN bit in the
DBRFCNT0 register is cleared to 0.).