11. Local Bus State Controller (LBSC)

Rev.1.00 Jan. 10, 2008 Page 419 of 1658

REJ09B0261-0100

Bus (Bits)
Read/
Write
Access
(bits)*1
Odd/
Even IOIS16 Access CE2 CE1 A0 D15 to D8 D7 to D0
Write 8 Even H ⎯ H L L Invalid Write data
Odd H First L H H Invalid Write data
Dynamic
Bus
Sizing*2
Odd H Second H L H Invalid Write data
16 Even H First L L L Upper write data Lower write data
Even H Second H L H Invalid Upper write data
Odd H ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8 Even × ⎯ L H L Invalid Read data
Odd × ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
ATA
comple-
ment mode
16 Even × ⎯ H L L Upper read data Lower read data
Read
(does
not
output
DACK) Odd × ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8 Even × ⎯ L H L Invalid Write data
Odd × ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
16 Even × ⎯ H L L Upper write data Lower write data
Write
(does
not
output
DACK) Odd × ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8 Even × ⎯ H H L Invalid Read data
Odd × ⎯ H H L Read data Invalid
16 Even × ⎯ H H H Upper read data Lower read data
Read
(outputs
DACK)
Odd × ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8 Even × ⎯ H H L Invalid Write data
Odd × ⎯ H H L Write data Invalid
Write
(outputs
DACK)
16 Even × ⎯ H H H Upper write data Lower write data
Odd × ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Legend:

×: Don't care

L: Low level

H: High level

Notes: 1. In 32-bit/64- bit/16-byte/32-byte transfer, the address is automatically incremented by the bus width, and the above accesses are repeated until the transfer data size is reached. 2. PCMCIA I/O card interface only.