Renesas SH7781 - page 121

5. Exception Handling
Rev.1.00 Jan. 10, 2008 Page 91 of 1658
REJ09B0261-0100
5.2.2 Exception Event Register (EXPEVT)
The exception event register (EXPEVT) consists of a 12-bit exception code. The exception code
set in EXPEVT is that for a reset or general exception event. The exception code is set
automatically by hardware when an exception occurs. EXPEVT can also be modified by software.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit:
0000000000000000
0000000/100000
Initial value:
RRRRRRRRRRRRRRRR
R/W R/W
EXPCODE
R/W R/W R/W R/W R/W R/W
R/W:
Bit:
Initial value:
R/W:
1514131211109876543210
0000
R R R R R/W R/W R/W R/W
Bit Bit Name
Initial
Value R/W Description
31 to 12 ⎯ All 0 R Reserved
For details on reading/writing this bit, see General
Precautions on Handling of Product.
11 to 0 EXPCODE H'000 or
H'020
R/W Exception Code
The exception code for a reset or general exception is
set. For details, see table 5.3.