Rev.1.00 Jan. 10, 2008 Page xxvi of xxx
REJ09B0261-0100
26.4 Operation......................................................................................................................... 1314
26.4.1 Bus Format....................................................................................................... 1314
26.4.2 Non-Compressed Modes.................................................................................. 1315
26.4.3 Compressed Modes...........................................................................................1324
26.4.4 Operation Modes.............................................................................................. 1327
26.4.5 Transmit Operation........................................................................................... 1328
26.4.6 Receive Operation............................................................................................ 1331
26.4.7 Serial Clock Control......................................................................................... 1334
26.5 Usage Note.......................................................................................................................1335
26.5.1 Restrictions when an Overflow Occurs during Receive DMA Operation........ 1335
26.5.2 Pin Function Setting for the SSI Module..........................................................1335
26.5.3 Usage Note in Slave Mode............................................................................... 1335
Section 27 NAND Flash Memory Controller (FLCTL)..........................................1337
27.1 Features............................................................................................................................1337
27.2 Input/Output Pins............................................................................................................. 1340
27.3 Register Descriptions....................................................................................................... 1342
27.3.1 Common Control Register (FLCMNCR)......................................................... 1344
27.3.2 Command Control Register (FLCMDCR)........................................................1346
27.3.3 Command Code Register (FLCMCDR)........................................................... 1348
27.3.4 Address Register (FLADR).............................................................................. 1349
27.3.5 Address Register 2 (FLADR2)......................................................................... 1351
27.3.6 Data Counter Register (FLDTCNTR).............................................................. 1352
27.3.7 Data Register (FLDATAR).............................................................................. 1353
27.3.8 Interrupt DMA Control Register (FLINTDMACR)......................................... 1354
27.3.9 Ready Busy Timeout Setting Register (FLBSYTMR)..................................... 1359
27.3.10 Ready Busy Timeout Counter (FLBSYCNT)...................................................1360
27.3.11 Data FIFO Register (FLDTFIFO).....................................................................1361
27.3.12 Control Code FIFO Register (FLECFIFO).......................................................1362
27.3.13 Transfer Control Register (FLTRCR)...............................................................1363
27.4 Operation......................................................................................................................... 1364
27.4.1 Operating Modes.............................................................................................. 1364
27.4.2 Command Access Mode................................................................................... 1364
27.4.3 Sector Access Mode......................................................................................... 1368
27.4.4 Status Read....................................................................................................... 1371
27.5 Example of Register Setting............................................................................................ 1373
27.6 Interrupt Processing......................................................................................................... 1376
27.7 DMA Transfer Settings....................................................................................................1376