Renesas SH7781 32.3.13 SIOF Module Signal Timing Table 32.18 SIOF Module Signal Timing , Figure 32.50 SIOF_MCLK Input Timing

32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1609 of 1658
REJ09B0261-0100
32.3.13 SIOF Module Signal Timing
Table 32.18 SIOF Module Signal Timing
Item Symbol Min. Max. Unit Figure
SIOF_MCLK clock input cycle time tMCYC t
pcyc — ns 32.50
SIOF_MCLK input high level width tMWH 0.4 × tMCYC — ns
SIOF_MCLK input low level width tMWL 0.4 × tMCYC — ns
SIOF_SCK clock cycle time tSICYC t
pcyc — ns 32.51 to 32.55
SIOF_SCK output high level width tSWHO 0.4 × tSICYC — ns 32.51 to 32.54
SIOF_SCK output low level width tSWLO 0.4 × tSICYC — ns
SIOF_SYNC output delay time tFSD — 10 ns
SIOF_SCK input high level width tSWHI 0.4 × tSICYC — ns 32.55
SIOF_SCK input low level width tSWLI 0.4 × tSICYC — ns
SIOF_SYNC input setup time tFSS 10 — ns
SIOF_SYNC input hold time tFSH 10 — ns
SIOF_TXD output delay time tSTDD — 10 ns 32.51 to 32.55
SIOF_RXD input setup time tSRDS 10 — ns
SIOF_RXD input hold time TSRDH 10 — ns
t
MCYC
SIOF_MCLK
t
MWH
t
MWL
Figure 32.50 SIOF_MCLK Input Timing