Renesas SH7781 - page 1011

20. Graphics Data Translation Accelerator (GDTA)
Rev.1.00 Jan. 10, 2008 Page 981 of 1658
REJ09B0261-0100
20.3.3 GA Interrupt Source Indicating Register (GACISR)
GACISR is in the GDTA common register block and indicates the states of interrupt sources for
each module.
161718192021222324252627282931 30
0000000000000000
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
BIt:
Initial value:
R/W:
01234567891011121315 14
0000000000000000
CL_ENDMC_ENDCL_ERRMC_ERR ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
RRRR⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 4 ⎯ All 0 ⎯ Reserved
These bits are always read as 0. The write value should
always be 0.
3 MC_EER 0 R Indicates whether an MC module error interrupt has
occurred.
0: No error
1: Error occurred
2 CL_EER 0 R Indicates whether a CL module error interrupt has
occurred.
0: No error
1: Error occurred
1 MC_END 0 R Indicates whether an MC module processing end
interrupt has occurred.
0: '1' has been written to the MC_ENCR bit in GACICR.
1: Processing completed
0 CL_END 0 R Indicates whether a CL module processing end interrupt
has occurred.
0: '1' has been written to the CL_ENCR bit in GACICR.
1: Processing completed
Note: MC processing completion is indicated when the command processing is complete and the
end command is written to the MC command FIFO (see section 20.3.17, CL Input Y
Padding Size Setting Register (CLIYPR)).