Renesas SH7781 - page 282

9. On-Chip Memory
Rev.1.00 Jan. 10, 2008 Page 252 of 1658
REJ09B0261-0100
9.2.4 OL memory Transfer Destination Address Register 0 (LDA0)
When MMUCR.AT = 0 or RAMCR.RP = 0, LDA0 specifies the transfer destination physical
address for block transfer to page 0A or 0B of the OL memory.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit :
000
Initial value :
R R R R/W R/W R/W R/W R/W R/W R/W
L0DADR
L0DADR L0DSZ
R/W R/W R/W R/W R/W R/W
R/W:
1514131211109876543210
Bit :
0000
Initial value :
R/WR/WR/WR/WR/WR/WRRRRR/WR/WR/WR/WR/WR/W
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 29 — All 0 R Reserved
For read/write in these bits, refer to General
Precautions on Handling of Product.
28 to 10 L0DADR Undefined R/W OL memory Page 0 Block Transfer Destination Address
When MMUCR.AT = 0 or RAMCR.RP = 0, these bits
specify transfer destination physical address for block
transfer to page 0A or 0B in the OL memory.
9 to 6 — All 0 R Reserved
For read/write in these bits, refer to General
Precautions on Handling of Product.