Appendix
Rev.1.00 Jan. 10, 2008 Page 1632 of 1658
REJ09B0261-0100
Reset
Pin Name
(LSI level)
Pin Name
(Module level)
Related
Module I/O
Power
-on Manual Sleep
Module
Standby
Bus
Release
DACK0 Port K1(default) GPIO I/O PI K K K
DACK0 DMAC O O O K O
Port K0 (default) GPIO I/O PI K K K DACK1
DACK1 DMAC O O O K O
Port K5 (default) GPIO I/O PI K K K
DACK2 DMAC O O O O O
SCIF2_TXD SCIF O PZ/Z O O O
MMCCMD MMCIF I/O PI/I K K K
DACK2/
SCIF2_TXD/
MMCCMD/
SIOF_TXD
SIOF_TXD SIOF O
H K K K
Port K4 (default) GPIO I/O PI K K K
DACK3 DMAC O O O O O
SCIF2_SCK SCIF I/O I K K K
MMCDAT MMCIF I/O I K K K
DACK3/
SCIF2_SCK/
MMCDAT/
SIOF_SCK
SIOF_SCK SIOF I/O
L K K K
STATUS0
(default)
RESET O H H L H L
DRAK0 DMAC O O O O O
STATUS0/
DRAK0
Port K7 GPIO I/O K K K K
STATUS1
(default)
RESET O H H H L L
DRAK1 DMAC O O O O O
STATUS1/
DRAK1
Port K6 GPIO I/O K K K K
DRAK2/CE2A Port L5 (default) GPIO I/O PI K K K K
DRAK2 DMAC O O O O O
CE2A LBSC O K K K K