Appendix
Rev.1.00 Jan. 10, 2008 Page 1651 of 1658
REJ09B0261-0100
Pin Name (LSI level)
Pin Name
(Module level) Module I/O When Not in Use
Port J6 (default) GPIO I/O
SIOF_TXD SIOF O
HAC0_SDOUT HAC O
SIOF_TXD/
HAC0_SDOUT/
SSI0_SDATA
SSI0_SDATA SSI I/O
Open
Port J1 (default) GPIO I/O
HAC1_BITCLK HAC I
HAC1_BITCLK/
SSI1_CLK
SSI1_CLK SSI I
Open
Port J7 (default) GPIO I/O
SCIF5_TXD SCIF O
HAC1_SYNC HAC O
SCIF5_TXD/
HAC1_SYNC/
SSI1_WS
SSI1_WS SSI I/O
Open
Port N7 GPIO I/O
SCIF5_RXD SCIF I
HAC1_SDIN HAC I
SCIF5_RXD/
HAC1_SDIN/
SSI1_SCK
SSI1_SCK SSI I/O
Open
Port N6 GPIO I/O
SCIF5_SCK SCIF I/O
HAC1_SDOUT HAC O
SCIF5_SCK/
HAC1_SDOUT/
SSI1_SDATA
SSI1_SDATA SSI I/O
Open
THDAG THDAG Connected to VSS
THDAS THDAS Connected to VSS
THDCTL THDCTL Connected to VSS
THDCD THDCD Connected to VSS
VDDQ-TD VDDQ-TD Connected to VSS or VDDQ
ASEBRK/
BRKACK
ASEBRK/
BRKACK
H-UDI I/O Open
TCK TCK H-UDI I Open
TRST TRST H-UDI I Pulled-down to VSS or
connected to PRESET*4
TDI TDI H-UDI I Open
TMS TMS H-UDI I Open
TDO TDO H-UDI O Open