Renesas SH7781 9.2 Register Descriptions

9. On-Chip Memory
Rev.1.00 Jan. 10, 2008 Page 246 of 1658
REJ09B0261-0100
9.2 Register Descriptions
The following registers are related to the on-chip memory.
Table 9.4 Register Configuration
Name Abbreviation R/W P4 Address*
Area 7
Address* Access Size
On-chip memory control
register
RAMCR R/W H'FF00 0074 H'1F00 0074 32
OL memory transfer source
address register 0
LSA0 R/W H'FF00 0050 H'1F00 0050 32
OL memory transfer source
address register 1
LSA1 R/W H'FF00 0054 H'1F00 0054 32
OL memory transfer
destination address register
0
LDA0 R/W H'FF00 0058 H'1F00 0058 32
OL memory transfer
destination address register
1
LDA1 R/W H'FF00 005C H'1F00 005C 32
Note: * The P4 address is the address used when using P4 area in the virtual address space.
The area 7 address is the address used when accessing from area 7 in the physical
address space using the TLB.
Table 9.5 Register States in Each Processing Mode
Name Abbreviation
Power-On
Reset Manual Reset Sleep Standby
On-chip memory control
register
RAMCR H'0000 0000 H'0000 0000 Retained Retained
OL memory transfer source
address register 0
LSA0 Undefined Undefined Retained Retained
OL memory transfer source
address register 1
LSA1 Undefined Undefined Retained Retained
OL memory transfer
destination address register
0
LDA0 Undefined Undefined Retained Retained
OL memory transfer
destination address register
1
LDA1 Undefined Undefined Retained Retained