32. Electrical Characteristics

Rev.1.00 Jan. 10, 2008 Page 1578 of 1658

REJ09B0261-0100

A25 to A0
D31 to D0
D31 to D0
(Write)
(Read)
(SA: IO memory)
(SA: IO memory)

Legend:

IO: DACK device
SA: Single-address DMA transfer
DA: Dual-address DMA transfer
Note: DACK is configured as active-high.
t
WDD
t
WDD
t
WDD
t
DACDF
t
DACDF
t
DACD
t
DACD
t
DACD
TS1
t
AD
T1 T2 TH1
t
AD
t
RDH
t
RDS
t
CSD
t
RWD
t
RWD
t
CSD
t
RSD
t
RSD
t
RSD
t
WED1
t
WEDF
t
WEDF
t
BSD
t
BSD
t
DACD
t
DACD
CLKOUT
RD/WR
CSn
WEn
BS
RDY
RD
DACKn
DACKn
DACKn
(DA)
Figure 32.12 SRAM Bus Cycle: Basic Bus Cycle (CSnWCR.IW = 0000, CSnWCR.RDS = 001, CSnWCR.WTS = 001, CSnWCR.RDH = 001, CSnWCR.WTH = 001)