10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 310 of 1658
REJ09B0261-0100
(4) Interrupt Mask Register (INT2MSKR) INT2MSKR is a 32-bit readable/writable register that can mask interrupts for sources indicated in the interrupt source register. When a bit in this register is set to 1, the interrupt in the corresponding bit is not notified. INT2MSKR is initialized to H'FFFF FFFF (all masked) by a reset. After this register is written to or the masking is cleared by writing to INT2MSKCLR, the timing required to reflect the register value is guaranteed by reading from this register once.
161718192021222324252627282931 30
1111111111111111
⎯⎯
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WRRR
Bit:
Initial value:
R/W:
01234567891011121315 14
1111111111111111
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W R/W
Bit:
Initial value:
R/W:
Table 10.9 shows the correspondence between bits in INT2MSKR and the interrupts that are masked. Table 10.9 Correspondence between Bits in INT2MSKR and Interrupts that Are Masked
Bit
Initial
Value R/W Source Function Description
31 to
29
All 1 R Reserved These bits are always read as 1.
The write value should always be 1.
28 1 R/W GDTA Masks GDTA interrupt
27 1 R/W DU Masks DU interrupt
26 1 R/W SSI channel 1 Masks the SSI channel 1 interrupt
25 1 R/W SSI channel 0 Masks the SSI channel 0 interrupt
24 1 R/W GPIO Masks the GPIO interrupt
23 1 R/W FLCTL Masks the FLCTL interrupt
22 1 R/W MMCIF Masks the MMCIF interrupt
21 1 R/W HSPI Masks the HSPI interrupt
Masks interrupt of each
on-chip peripheral
module
[When written]
0: Invalid
1: Interrupt is masked
[When read]
0: Not masked
1: Masked
20 1 R/W SIOF Masks the SIOF interrupt
19 1 R/W PCIC (5) Masks PCIERR and PCIPWD3 to
PCIPWD0 interrupt