Renesas SH7781 - page 1152

22. Serial I/O with FIFO (SIOF)
Rev.1.00 Jan. 10, 2008 Page 1122 of 1658
REJ09B0261-0100
22.3.10 Clock Select Register (SISCR)
SISCR is a 16-bit readable/writable register that sets the serial clock generation conditions for the
master clock. SCSCR can be specified when the TRMD1 and TRMD0 bits in SIMDR are set to
B'10 or B'11.
01234567891011121315 14
0000000000000011
BRDV[2:0]—————BRPS[4:0]—
MSSELMSIMM
R/WR/WR/WRRRRRR/WR/WR/WR/WR/WRR/W R/W
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
15 MSSEL 1 R/W Master Clock Source Selection
The master clock is the clock source input to the baud
rate generator.
0: Uses the input signal of the SIOF_MCLK pin as the
master clock
1: Uses a peripheral clock (Pck) as the master clock
14 MSIMM 1 R/W Master Clock Direct Selection
0: Uses the output clock of the baud rate generator as
the serial clock
1: Uses the master clock itself as the serial clock
13 — 0 R Reserved
This bit is always read as 0. The write value should
always be 0.
12 to 8 BRPS[4:0] 00000 R/W Prescaler Setting
These bits set the master clock division ratio according
to the count value of the prescaler of the baud rate
generator.
The range of settings is from B'00000 (× 1/1) to B'11111
(× 1/32).
7 to 3 — All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.