11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 429 of 1658
REJ09B0261-0100
Tm1 Tm1
CLKOUT
RD/FRAME
CSn
R/W
D63 to D0
BS
Tmd1w Tmd1
RDY
DACK
AD0A
Figure 11.24 MPX Interface Timing 1 (Single Read Cycle, IW = 0000, No External Wait, 64-Bit Bus Width)