13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 594 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
19 to 1 All 0 SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.
0 MBARE 0 SH: R/W
PCI: R
PCI Memory Base Address Register 0 Enable
Enables accesses to the local address space 0 by
setting this bit to 1.
0: MBAR0 disabled
1: MBAR0 enabled
(3) PCI Local Space Register 1 (PCILSR1) See section 13.4.4 (1), Accessing Memory Space in This LSI.
SH R/W:
PCI R/W:
RRRRR/WR/WR/WR/WR/WR/WR/WR/WR/WRRR
RRRRRRRRRRRRRRRR
SH R/W:
PCI R/W:
161718192021222324252627282931 30
0000000000000000
LSR——
Bit:
Initial value:
R/WRRRRRRRRRRRRRRR
RRRRRRRRRRRRRRR R
0000000000000000
MBA
RE
— —
01234567891011121315 14Bit:
Initial value:
Bit Bit Name
Initial
Value R/W Description
31 to 29 All 0 SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.