11. Local Bus State Controller (LBSC)

Rev.1.00 Jan. 10, 2008 Page 430 of 1658

REJ09B0261-0100

Tm1
CLKOUT
A
RD/FRAME
CSn
R/W
D63 to D0
BS
Tmd1w Tmd1w Tmd1
RDY
DACKn
D0
In this example, DACKn is active-high. The circles indicate the sampling timing.
Figure 11.25 MPX Interface Timing 2 (Single Read, IW = 0000, One External Wait Inserted, 64-Bit Bus Width)