Rev.1.00 Jan. 10, 2008 Page xii of xxx
REJ09B0261-0100
7.8.1 Overview of 32-Bit Address Extended Mode.....................................................199
7.8.2 Transition to 32-Bit Address Extended Mode.................................................... 200
7.8.3 Privileged Space Mapping Buffer (PMB) Configuration................................... 200
7.8.4 PMB Function.....................................................................................................202
7.8.5 Memory-Mapped PMB Configuration............................................................... 203
7.8.6 Notes on Using 32-Bit Address Extended Mode................................................ 204
7.9 32-Bit Boot Function......................................................................................................... 207
7.9.1 Initial Entries to PMB.........................................................................................207
7.9.2 Notes on 32-Bit Boot.......................................................................................... 207
7.10 Usage Notes....................................................................................................................... 209
7.10.1 Note on Using LDTLB Instruction..................................................................... 209
Section 8 Caches...................................................................................................................211
8.1 Features..............................................................................................................................211
8.2 Register Descriptions......................................................................................................... 215
8.2.1 Cache Control Register (CCR)........................................................................... 216
8.2.2 Queue Address Control Register 0 (QACR0).....................................................218
8.2.3 Queue Address Control Register 1 (QACR1).....................................................219
8.2.4 On-Chip Memory Control Register (RAMCR).................................................. 220
8.3 Operand Cache Operation..................................................................................................222
8.3.1 Read Operation................................................................................................... 222
8.3.2 Prefetch Operation.............................................................................................. 223
8.3.3 Write Operation.................................................................................................. 224
8.3.4 Write-Back Buffer.............................................................................................. 225
8.3.5 Write-Through Buffer.........................................................................................225
8.3.6 OC Two-Way Mode........................................................................................... 226
8.4 Instruction Cache Operation.............................................................................................. 227
8.4.1 Read Operation................................................................................................... 227
8.4.2 Prefetch Operation.............................................................................................. 227
8.4.3 IC Two-Way Mode.............................................................................................228
8.4.4 Instruction Cache Way Prediction Operation..................................................... 228
8.5 Cache Operation Instruction.............................................................................................. 229
8.5.1 Coherency between Cache and External Memory..............................................229
8.5.2 Prefetch Operation.............................................................................................. 231
8.6 Memory-Mapped Cache Configuration............................................................................. 232
8.6.1 IC Address Array................................................................................................232
8.6.2 IC Data Array..................................................................................................... 234
8.6.3 OC Address Array.............................................................................................. 234
8.6.4 OC Data Array....................................................................................................236
8.6.5 Memory-Mapped Cache Associative Write Operation.......................................237