Appendix
Rev.1.00 Jan. 10, 2008 Page 1633 of 1658
REJ09B0261-0100
Reset
Pin Name
(LSI level)
Pin Name
(Module level)
Related
Module I/O
Power
-on Manual Sleep
Module
Standby
Bus
Release
Port K3 (default) GPIO I/O PI K K K DREQ0
DREQ0 DMAC I PI/I PI/I PI/I PI/I
Port K2 (default) GPIO I/O PI K K K DREQ1
DREQ1 DMAC I PI/I PI/I PI/I PI/I
Port L7 (default) GPIO I/O PI K K K
DREQ2 DMAC I PI/I PI/I PI/I PI/I
DREQ2/INTB
INTB PCIC I K K K
Port L6 (default) GPIO I/O PI K K K
DREQ3 DMAC I PI/I PI/I PI/I PI/I
DREQ3/INTC
INTC PCIC I K K K
MCLK[1:0] MCLK[1:0] DBSC2 O L K K K
MCLK[1:0] MCLK[1:0] DBSC2 O L K K K
MDQS[3:0] MDQS[3:0] DBSC2 I/O Z K K K
MDQS[3:0] MDQS[3:0] DBSC2 I/O Z K K K
MDM[3:0] MDQ[3:0] DBSC2 O H K K K
MDQ[31:0] MDQ[31:0] DBSC2 I/O Z K K K
MCKE MCKE DBSC2 O L K K K
MCAS MCAS DBSC2 O L K K K
MRAS MRAS DBSC2 O L K K K
MCS MCS DBSC2 O L K K K
MWE MWE DBSC2 O L K K K
MODT MODT DBSC2 O L K K K
MA[14:0] MA[14:0] DBSC2 O L K K K
MBA[2:0] MBA[2:0] DBSC2 O L K K K
MBKPRST MBKPRST DBSC2 I I K K K