1. Overview
Rev.1.00 Jan. 10, 2008 Page 6 of 1658
REJ09B0261-0100
Item Features
Local bus state
controller (LBSC)
A dedicated Local-bus interface
Controls the external memory space divided into seven 64-Mbyte
(max.) areas
The interface type, bus width, and wait-cycle insertion can be set for
each area.
SRAM interface
Wait-cycle insertion can be set by register values.
Wait-cycle insertion by the RDY pin
Connectable as area 0, 1, 2, 3, 4, 5, or 6
Selectable bus width: 64-/32-/16-/8-bit
Burst ROM interface
Wait-cycle insertion can be set by register values.
Number of units in burst transfers can be set by register values.
Connectable as area 0, 1, 2, 3, 4, 5, or 6
Selectable bus width: 64-/32-/16-/8-bit
MPX interface
Address/data multiplexing
Connectable as area 1 or 4
Selectable bus widths: 64-/32-bit
SRAM interface with byte-control
Connectable as area 1 or 4
Selectable bus width: 64-/32-/16-bit
PCMCIA interface (only for little-endian mode)
Wait-cycle insertion can be set by register values.
Bus-sizing function for adaptation to the I/O bus width
Connectable as area 5 or 6
Selectable bus width: 16-/8-bit
Supports transfer to and from E-IDE/ATAPI devices (ATA3)
Supports PIO mode 4 type and multi-word DMA mode 2 type
Connectable as area 5 or 6
Big or little endian is selectable