Appendix
Rev.1.00 Jan. 10, 2008 Page 1628 of 1658
REJ09B0261-0100

B. Mode Pin Settings

The MODE14–MODE0 pin values are input in the event of a power-on reset via the PRESET pin.

Note: The MODE6 pin is output state after power-on reset.

Legend:

H: High level input

L: Low level input

Table B.1 Clock Operating Modes with External Pin Combination

Pin Value
MODE [4:0]
Pin Number
OSC/
External
input
Frequency
[MHz]
Frequency
(vs. Input Clock)
Clock
Operating
Mode 4 3 2 1 0 Min Max
Divider
1
PLL
1 Ick Uck SHck GAck DUck Pck DDRck Bck
0 L L L L L × 36 × 18 × 18 × 9 × 9 × 3 × 18 × 6
1 L L L L H × 36 × 18 × 18 × 9 × 9 × 3/2 × 18 × 3/2
2 L L L H L × 36 × 12 × 12 × 6 × 6 × 3 × 12 × 6
3 L L L H H
12 17 × 1
× 36 × 12 × 12 × 6 × 6 × 3/2 × 12 × 3/2
16 H L L L L 23 34 × 1 × 36 × 18 × 9 × 9 × 9/2 × 9/2 × 3/2 × 9 × 3
17 H L L L H × 18 × 9 × 9 × 9/2 × 9/2 × 3/4 × 9 × 3/4
18 H L L H L × 18 × 6 × 6 × 3 × 3 × 3/2 × 6 × 3
19 H L L H H × 18 × 6 × 6 × 3 × 3 × 3/4 × 6 × 3/4

Note: When MODE12 or MODE11 is set to low level, DUck is stopped.

The division ratio of the divider 2 can be read out from FRQMR1.

For details, see section 15, Clock Pulse Generator (CPG).