23. Serial Peripheral Interface (HSPI)

Rev.1.00 Jan. 10, 2008 Page 1168 of 1658

REJ09B0261-0100

Data transfer cycle
HSPI_CLK (CLKP = 0)
HSPI_CLK (CLKP = 1)
1 432 8765
MSB 6 5 4 3 2 1 LSB
MSB 6 5 4 3 2 1 LSB
*
HSPI_TX
HSPI_RX
HSPI_CX
Figure 23.5 Timing Conditions when FBS = 1
HSPI_CLK (CLKP = 0)
HSPI_CLK (CLKP = 1)
1 8..2 9 16..10
HSPI_TX MSB 6 LSB MSB 6 LSB
MSB 6 LSB MSB 6* * LSB
HSPI_RX
HSPI_CS
Data transfer cycle
Figure 23.6 Timing Conditions when FBS = 1 (Continuous Transfer) The asterisk (*) in the figures shows 0 or 1.