31. Register List

Rev.1.00 Jan. 10, 2008 Page 1560 of 1658

REJ09B0261-0100

Table 31.8 States of the Registers in the Individual Operating Modes (7)
Module
Name Name Abbrev.
Power-on
Reset by
PRESET Pin/
WDT/H-UDI
Manual Reset
by
WDT/Multiple
Exception
Sleep/
Deep Sleep by
SLEEP
Instruction
UBC Match condition setting register 0 CBR0 H'20000000 Retained Retained
Match operation setting register 0 CRR0 H'00002000 Retained Retained
Match address setting register 0 CAR0 Undefined Retained Retained
Match address mask setting register 0 CAMR0 Undefined Retained Retained
Match condition setting register 1 CBR1 H'20000000 Retained Retained
Match operation setting register 1 CRR1 H'00002000 Retained Retained
Match address setting register 1 CAR1 Undefined Retained Retained
Match address mask setting register 1 CAMR1 Undefined Retained Retained
Match data setting register 1 CDR1 Undefined Retained Retained
Match data mask setting register 1 CDMR1 Undefined Retained Retained
Execution count break register 1 CETR1 Undefined Retained Retained
Channel match flag register CCMFR H'00000000 Retained Retained
Break control register CBCR H'00000000 Retained Retained
Table 31.9 States of the Registers in the Individual Operating Modes (8)
Module
Name Name Abbrev.
Power-on
Reset by
PRESET Pin/
WDT/H-UDI
Manual Reset
by
WDT/Multiple
Exception
Sleep/
Deep Sleep by
SLEEP
Instruction
Module
Standby
H-UDI Instruction register SDIR H'0EFF Retained Retained Retained
Interrupt source register SDINT H'0000 Retained Retained Retained