7. Memory Management Unit (MMU)

Rev.1.00 Jan. 10, 2008 Page 197 of 1658

REJ09B0261-0100

Address field
Data field
PPN:
V:
E:
SZ:
D:
*
:
Physical page number
Validity bit
Entry
Page size bits
Dirty bit
Don't care
PR:
C:
SH:
WT:
:
Protection key data
Cacheability bit
Share status bit
Write-through bit
Reserved bits
(write value should be 0
and read value is undefined )
31 21
21
0
V
109872928 4 365
PR CPPN D
SZ1
SH
WT
31 0
111101110000 00E
1920 8 71413
******
** ****
Figure 7.23 Memory-Mapped UTLB Data Array (TLB Compatible Mode) 7.7.6 UTLB Data Array (TLB Extended Mode) In TLB extended mode, the names of the data arrays have been changed from UTLB data array to UTLB data array 1, UTLB data array 2 is added, and the EPR and ESZ bits are accessible. In TLB extended mode, the PR and SZ bits of UTLB data array 1 are reserved and 0 should be specified as the write value for these bits. In addition, when a write to UTLB data array 1 is performed, a write to UTLB data array 2 of the same entry should always be performed after that. In TLB compatible mode (MMUCR.ME = 0), UTLB data array 2 cannot be accessed. Operation if they are accessed is not guaranteed. (1) UTLB Data Array 1 In TLB extended mode, bits 7 to 4 in the data field, which correspond to the PR and SZ bits in compatible mode, are reserved. Specify 0 as the write value for these bits.
Legend:
Address field
Data field
PPN:
V:
E:
D:
*:
Physical page number
Validity bit
Entry
Dirty bit
Don't care
C:
SH:
WT:
:
Cacheability bit
Share status bit
Write-through bit
Reserved bits
(write value should be 0,
and read value is undefined)
31 210
V
109872928
21
43
CDPPN
31 0
00
11110111
0
00
0
E
2019 8 71413
WTSH
******
*** ***
Figure 7.24 Memory-Mapped UTLB Data Array 1 (TLB Extended Mode)