11. Local Bus State Controller (LBSC)

Rev.1.00 Jan. 10, 2008 Page 415 of 1658

REJ09B0261-0100

*2
TAS1 TS1 TB2 TB1 TB2 TB1 TB1T1 TB2 T2 TAH1TH1
CLKOUT
A25 to A5
A4 to A0
CSn
R/W
RD
D31 to D0
(In reading)
BS
RDY
DACKn *1
Notes: 1. In this example, DACKn is active-high.
2. When RDSPL in CSnBCR is set to 1.
Figure 11.14 Burst ROM Wait Timing