23. Serial Peripheral Interface (HSPI)

Rev.1.00 Jan. 10, 2008 Page 1152 of 1658

REJ09B0261-0100

Figure 23.1 is a block diagram of the HSPI.
HSPI_CLK
HSPI_TX
HSPI_RX LSB MSB
SPCR
HSPI_CS
SPSR
SPSCR
SPTBR
SPRBR
Pck
In FIFO mode
Peripheral bus
Transmit FIFO
Receive FIFO
(Eight entries
for each)
LSB MSB
Bus interface
Registers
System
control
Shift register
Clock division
Polarity selection SCK generator
Figure 23.1 Block Diagram of HSPI