11. Local Bus State Controller (LBSC)

Rev.1.00 Jan. 10, 2008 Page 404 of 1658

REJ09B0261-0100

T1
CLKOUT
A25 to A0
CSn
R/W
RD
D31 to D0
(In reading)
WEn
D31 to D0
(In writing)
BS
T2
RDY
DACKn
In this example, DACKn is high-active.
Figure 11.5 Basic Timing of SRAM Interface