10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 340 of 1658
REJ09B0261-0100

10.6 Interrupt Response Time

Table 10.14 shows response time. The response time is the interval from generation of an interrupt

request until the start of interrupt exception handling and until fetching of the first instruction of

the exception handling routine.

Table 10.14 Interrupt Response Time

Number of States
Peripheral Modules
Item NMI IRL IRQ
Other than
GPIO/PCIC GPIO/PCIC Remarks
Priority
determination time
6Bcyc +
2Pcyc
8Bcyc +
2Pcyc
4Bcyc +
2Pcyc
5Pcyc 7Pcyc
Wait time until the
CPU finishes the
current sequence
S-1 (0)
× Icyc
Interval from the
start of interrupt
exception handling
(saving SR and PC)
until a SuperHyway
bus request is issued
to fetch the first
instruction of the
exception handling
routine
11Icyc
+ 1Scyc
Response
time
Total (S + 10) Icyc
+ 1Scyc
+ 5Bcyc
+ 2Pcyc
(S + 10) Icyc
+ 1Scyc
+ 8Bcyc
+ 2Pcyc
(S + 10) Icyc
+ 1Scyc
+ 4Bcyc
+ 2Pcyc
(S + 10) Icyc
+ 1Scyc
+ 5Pcyc
(S + 10) Icyc
+ 1Scyc
+ 7Pcyc

Legend:

Icyc: Period of one CPU clock cycle

Scyc: Period of one SuperHyway clock cycle

Bcyc: Period of one bus clock cycle

Pcyc: Period of one peripheral clock cycle

S: Number of instruction execution states