7. Memory Management Unit (MMU)

Rev.1.00 Jan. 10, 2008 Page 179 of 1658

REJ09B0261-0100

The operation of the LDTLB instruction is shown in figures 7.16 and 7.17.
PPN [28:10]
PPN [28:10]
PPN [28:10]
SZ [1:0]
SZ [1:0]
SZ [1:0]
SH
SH
SH
C
C
C
PR [1:0]
PR [1:0]
PR [1:0]
ASID [7:0]
ASID [7:0]
ASID [7:0]
VPN [31:10]
VPN [31:10]
VPN [31:10]
V
V
V
Entry 0
Entry 1
Entry 2
D
D
D
WT
WT
WT
PPN [28:10] SZ [1:0] SH C PR [1:0]ASID [7:0] VPN [31:10] VEntry 63 D WT
31 2928 9 8 765 4 3 2 1 0
——
V
SZ1PR[1:0]SZ0
CDSH
WT
PTEL
Write
UTLB
31 109 87 0
— ASID
PTEH
31 26252423 18171615 10 9 87 3 2 1 0
LRUI — URB — URC SV TI— AT
MMUCR
VPN
10
PPN
Entry specification SQMD
Figure 7.16 Operation of LDTLB Instruction (TLB Compatible Mode)